The present invention relates to inspection of a sample for microscale pattern defects and foreign substances that involves comparison between images of the sample obtained with the use of illumination light, laser light, or electron beams and reference images. The invention relates particularly to an apparatus and a method for inspecting patterns suitable for external inspection of semiconductor wafers, TFTs (thin film transistors), photomasks, or the like.
One of the examples of conventional defect inspection methods involving comparison between images of an object to be inspected and reference images is disclosed in JP-A-05-264467 (Patent Document 1). In the method of Patent Document 1, a line sensor sequentially acquires images of an inspection object on which identical patterns are arranged regularly while the inspection object is moved. A particular image is then compared with an image obtained after a time interval during which the inspection object is moved by a pattern pitch, or the amount of space between two patterns. Defects are detected by detecting mismatched portions of the two images.
Such a conventional defect inspection method is further discussed below, based on the assumption that it is intended for inspection of semiconductor wafers. As shown in FIG. 2A, a sample 11 to be inspected, or a semiconductor wafer, has multiple identically-patterned chips 20 arranged thereon regularly. When the sample 11 is a memory element such as DRAM or the like, each of the chips 20 can be roughly classified into memory mats 20-1 and a peripheral circuitry area 20-2, as shown in FIG. 2B. Each of the memory mats 20-1 is a collection of tiny identical patterns (cells) whereas the peripheral circuitry area 20-2 is basically a collection of random patterns. Generally, the memory mats 20-1 are high in pattern density, and images acquired from those areas are dark. In contrast, the peripheral circuitry area 20-2 is low in pattern density, and images acquired therefrom are bright.
In a conventional pattern inspection, the inspection of the peripheral circuitry area 20-2 is such that images of mutually corresponding areas in adjacent chips (e.g., image areas 22 and 23 in FIG. 2A) are compared in terms of luminance and such that portions of those image areas with greater luminance differences than a threshold value are detected as defects. Such an inspection is hereinafter referred to as chip comparison. In contrast, the inspection of the memory mats 20-1 is such that images of adjacent cells within a memory mat 20-1 are compared in terms of luminance and such that portions of those images with greater luminance differences than a threshold value are detected as defects. Such an inspection is hereinafter referred to as cell comparison. The above two kinds of comparative inspections need be performed at high speed.